// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_nvme_global_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:12 Create file
// ******************************************************************************

#ifndef __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_FIELD_H__
#define __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_FIELD_H__

#define HIPCIEC_NVME_GLOBAL_REG_INT_COAL_EN_LEN     1
#define HIPCIEC_NVME_GLOBAL_REG_INT_COAL_EN_OFFSET  1
#define HIPCIEC_NVME_GLOBAL_REG_RO_REG_WR_EN_LEN    1
#define HIPCIEC_NVME_GLOBAL_REG_RO_REG_WR_EN_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_SRIOV_MODE_SEL_LEN    3
#define HIPCIEC_NVME_GLOBAL_REG_SRIOV_MODE_SEL_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_BAR0_DB_ATU_LOW_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_BAR0_DB_ATU_LOW_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_BAR0_DB_ATU_HIGH_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_BAR0_DB_ATU_HIGH_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF2_VF_BAR0_DB_ATU_LOW_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF2_VF_BAR0_DB_ATU_LOW_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF2_VF_BAR0_DB_ATU_HIGH_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF2_VF_BAR0_DB_ATU_HIGH_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_BAR0_DB_ATU_LOW_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_BAR0_DB_ATU_LOW_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_BAR0_DB_ATU_HIGH_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_BAR0_DB_ATU_HIGH_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_VF_BAR0_DB_ATU_LOW_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_VF_BAR0_DB_ATU_LOW_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_VF_BAR0_DB_ATU_HIGH_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_VF_BAR0_DB_ATU_HIGH_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_TIME_CNT_UNIT_LEN    16
#define HIPCIEC_NVME_GLOBAL_REG_TIME_CNT_UNIT_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK0_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK0_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK1_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK1_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK2_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK2_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK3_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK3_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING0_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING0_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING1_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING1_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING2_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING2_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING3_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING3_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK0_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK0_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK1_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK1_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK2_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK2_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK3_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK3_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING0_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING0_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING1_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING1_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING2_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING2_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING3_LEN    32
#define HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING3_OFFSET 0

#define HIPCIEC_NVME_GLOBAL_REG_PF3_CFG_INT_AGGRE_TIME_LEN    8
#define HIPCIEC_NVME_GLOBAL_REG_PF3_CFG_INT_AGGRE_TIME_OFFSET 24
#define HIPCIEC_NVME_GLOBAL_REG_PF3_CFG_INT_AGGRE_THR_LEN     8
#define HIPCIEC_NVME_GLOBAL_REG_PF3_CFG_INT_AGGRE_THR_OFFSET  16
#define HIPCIEC_NVME_GLOBAL_REG_PF0_CFG_INT_AGGRE_TIME_LEN    8
#define HIPCIEC_NVME_GLOBAL_REG_PF0_CFG_INT_AGGRE_TIME_OFFSET 8
#define HIPCIEC_NVME_GLOBAL_REG_PF0_CFG_INT_AGGRE_THR_LEN     8
#define HIPCIEC_NVME_GLOBAL_REG_PF0_CFG_INT_AGGRE_THR_OFFSET  0

#endif // __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_FIELD_H__
